Compiling problem opencl sdk using pipes.

Hello i tried to compile a kernel comunication using pipes. When i write the altera channel function i have the next error,Before using pipes i developed a first version using global memory but i want to reduce memory access comunicating kernels.

Part of the code :

# pragma unroll

for(int i=0;i<K;i++) //pipelined stage

A[i]=A[i+1];

A[K]=conv_out;

float B = A[0];

# pragma unroll

for(int i=0;i<K1*K1;i++)

{

int k_row = i/K_pool1;

int k_col = i%K_pool1;

if(B<A[(k_row*J)+k_col])

B = A[(k_row*J)+k_col];

}

write_channel_altera(c0,B);

}

}

the compiler message:

\device>aoc -c myfilter_v1.cl

******* Error: Assert failure at ..\..\..\..\llvm\lib\Target\FPGA\ChannelDepthIn

ference.cpp(281) *******

!pair.first && "multiple iowr sites" FAILED

Stack dump:

0. Program arguments: C:/altera/14.0/hld/windows64/bin/aocl-llc -march=fpga

-mattr=option3wrapper -fpga-const-cache=1 -board C:/altera/14.0/hld/board/teras

ic/de5net/hardware/de5net_a7/board_spec.xml myfilter_v1.bc -o myfilter_v1.v

1. Running pass 'Infer fifo depth of channels' on module 'myfilter_v1.bc'.

0x000000013F647854 (0x0000000002F9ED30 0x0000000002866038 0x0000000000D80A18 0x0

000000004B53780)

0x000000013F647D7E (0x0000000000000000 0x0000000000000000 0x0000000000D6C7E0 0x0

000000000000001)

0x0000000140727A48 (0x0000000000000008 0x0000000002F17500 0x0000000000000000 0x0

000000000D72BE0)

0x0000000140727D1B (0x0000000002F175B0 0x0000000000000002 0x0000000000D72BE0 0x0

00000014109BBD8)

0x000000013F3823E9 (0x0000000000000000 0x0000003256EBDC1A 0x0000000000000000 0x0

000000000000000)

0x00000001408B8A3E (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0

000000000000000), ??4_Init_locks@std@@QEAAAEAV01@AEBV01@@Z() + 0x642 bytes(s)

0x00000000774B5A4D (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0

000000000000000), BaseThreadInitThunk() + 0xD bytes(s)

0x00000000775EB831 (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0

000000000000000), RtlUserThreadStart() + 0x21 bytes(s)

Error: Verilog generator FAILED.