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:) but i think the OP is about inconsistent in simualtion and synthesis.
Cause I don't like Verilog i never check before for "Ignore Verilog initial constructs" for synthesis.
so when writing code for synthesis you should take in considaration some synthesis options and make assignment for it accordingly.
but if one want to power-up with '1' in register -> one should look for template in quartus text-editor.
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Yes, Modelsim follows your code virtually line by line. Synthesis does not as it has optimisation rules. My description above applies to synthesis be it VHDL or verilog.
If you have a constant you don't need register and so you don't need powerup value.
What I am saying is that if you apply reset followed by clock edge the synthesis respects your assignment, creates register and so is equivalent to modelsim. If you don't apply reset it does not (and issues warning) unless you ask to keep that using attributes to override the synthesis rules.
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