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Altera_Forum
Honored Contributor
Honored ContributorCompiler Problem
Dear all, Device : max II. The module function is to latch to 1 at the SignalIn risign edge. The code1 works well. As you know, there is an internal reset signal in MAX II device. so we ...
Altera_ForumHonored Contributor
Honored Contributor:) but i think the OP is about inconsistent in simualtion and synthesis.
Cause I don't like Verilog i never check before for "Ignore Verilog initial constructs" for synthesis. so when writing code for synthesis you should take in considaration some synthesis options and make assignment for it accordingly. but if one want to power-up with '1' in register -> one should look for template in quartus text-editor.
