Compiler Problem

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Dear all,

Device : max II.

The module function is to latch to 1 at the SignalIn risign edge. The code1 works well.

As you know, there is an internal reset signal in MAX II device. so we don't need to reset to 0;

So I write code 2, it works well in modelsim, but it will not work in Quartus.

In quartus , the bit is always 1. The reason is that quartus will optimize and will not see the default reset action.

So, how can i make the code 2 work correctly? perhaps iis there an option used to cahnge compiler action?

thanks;)

///////////////////////////////////////////

// code 1

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input wire nrst;

output reg bit;

always @ (negedge nrst, posedge signalin)

if (!nrst)

bit <= 0;

else

bit <= 1;

///////////////////////////////////////////

// code 2

///////////////////////////////////////////

output reg bit;

always @ (posedge signalin)

bit <= 1;

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code 1 has reset, code 2 has no reset so what is the problem.

The global powerup reset has nothing to do with code.