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Hi all,
I'm strugglin to figure out how to fix this error :
"Error (10822) : HDL error at rx_symb.vhd(30): could'nt implement registers for assignments on this clock edge "
from the code below which just takes the input array and passes it onto its output..
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx_symb is
port
(
-- Input ports
symb_in : in std_logic_vector(15 downto 0);
symb_clk : in std_logic;
-- Output ports
symb_out : out std_logic_vector(15 downto 0);
trigger : out std_logic :='0'
);
end rx_symb;
-- Library Clause(s) (optional)
-- Use Clause(s) (optional)
architecture struc of rx_symb is
-- Declarations (optional)
begin
process(symb_clk) is
begin
if rising_edge(symb_clk) then
symb_out <= symb_in;
trigger <= '1';
else
trigger <= '0';
end if;
end process;
end struc;
I've read a few of the older posts on this particular error and most were addressing the problem of giving a process conflicting clocks (ie either 2 different clocks or causing a statemet to be sensitive to different clock edges). As fr as I can tell, I dont have either of these issues in my code.
May you please shed some light.
Thank you.
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Hi Tiisetso,
you have a problem in your process description. At the rising edge of the clk you what to set the trigger signal to "1". But what should happend all the other time ? Setting the trigger signal to "0"? That is not the behaviour of an register, where the output signal could change only at the clock edge.
process(symb_clk) is
begin
if rising_edge(symb_clk) then
symb_out <= symb_in;
trigger <= '1';
else
trigger <= '0';
end if;
end process;
Kind regards
GPK
Honored Contributor
