Compiler error, not able to generate hardware

With such high logic utilization, and the fact that OpenCL on Arria 10 uses partial reconfiguration, I am not surprised your kernel is not routing. There is little to nothing you can do to avoid routing failures, other than making changes in your kernel to significantly reduce the logic utilization. In my experience, on Arria 10, successful routing in conjunction with partial reconfiguration becomes unlikely with over 60% logic utilization. I am not sure what you are doing that needs so much logic, though; unlike Stratix V, logic utilization is generally not a bottleneck on Arria 10, and I have managed to fill all of the DSPs and BRAMs on Arria 10 with ~50% logic utilization.

Regarding the lmem replication message, as discussed before, the compiler will replicate all the local memory buffers on the FPGA based on the number of accesses to the buffers, to allow all pipeline stages to be able to access the buffers in parallel. Then, the compiler performs a check after full replication and if it estimates that the kernel would fail to fit due to Block RAM overutilization, it restarts the compilation and instead of fully-parallel accesses, opts for sharing reads and write ports from/to the local memory buffers to reduce Block RAM utilization and allow the kernel to fit on the device. Of course this will come at the cost of lower performance due to pipeline stalls. To fix this problem, minimize the number of accesses to your buffers and make sure all the accesses are properly coalesced. You can also use the attributes described in "Intel FPGA SDK for OpenCL Best Practices Guide, Section 7.5" for more fine-grained control over the replication factor.