Compile errors with Qsys generated verilog

I am attaching an archive of the working C5G_LPDDR2_Nios_Test project. This is a demonstration project which comes with the Terasic Cyclone V GX Starter Kit CD (C5G_V.1.1.0_SystemCD). It was compiled in Quartus II 13.0 on the CD but initially did not compile or work with Quartus II 13.1.

I was able to get the demonstration application for Nios2 LPDDR2 SDRAM to work by using an Avalon-MM clock crossing bridge. However it did not work as it did with Quartus II 13.0. To get it to work, I exported the Avalon interfaces and connected them manually. The problem seems to have been that the waitrequest signal was a waitrequest_n on the LPDDR2 interface and a waitrequest (without the _n) on the Avalon-MM clock crossing bridge. By making the connections externally I was able to invert this signal to get it to work.

John