Compile errors with Qsys generated verilog

To build and successfully run the Eclipse gcc generated .elf test app for the C5G_LPDDR2_Nios_Test demonstration app in Quartus 13.1 I used the input CLOCK_125_p clock to directly drive the lpddr2 pll_ref_clk input. This is the only way the Nios2 generated verilog will compile to generate the .sof fpga Nios2 code. I also set the CLOCK_125_p PIN_U12 to Differential 1.2-V HSUL. Those modifications to the original demonstration project on the CD worked and the lpddr2 sdram test app ran successfully.