Compile errors with Qsys generated verilog

The bug appears to be in the qsys Verilog code generated. There is a symbol (dqs_busout) that is not defined as a wire or anything else but is used as an output for the capture_strobe_out parameter in the function call indicated in the first post of this thread.

I located the altera ip that seems to be used in generating the Verilog nios2:

c:/altera/13.1/ip/altera/altdq_dqs2/

Looks like the following files may be involved:

altdq_dqs2_acv_arriav_connect_to_hard_phy.sv

or

altdq_dqs2_acv_arriav_connect_to_hard_phy_lpddr2.sv

What do I modify to generate a 'wire dqs_busout;' declairation?