Compile errors with Qsys generated verilog

In Qsys 13.1 I added a LPDDR2 SDRAM Controller with UniPHY. This controller has a pll_sharing conduit which must be exported according to the following warning:

Warning: System.mem_if_lpddr2_emif: mem_if_lpddr2_emif.pll_sharing must be exported, or connected to a matching conduit.

I don't have any pins on my C5 GX Starter Kit board. The LPDDR2 signals are all present in the 'memory' conduit which I connected to the corresponding LPDDR2 pins. Is it safe to ignore this error? I think this may have something to do with the compile error I am getting and when I look at the C5G_LPDDR2_Nios_Test top level Verilog module it doesn't have any of the pll_shared signals in the C5G_QSYS module call.