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Altera_Forum
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12 years ago

Compile errors with Qsys generated verilog

Error (10162): Verilog HDL Object Declaration error at c5g_nios2_dram_daq_mem_if_lpddr2_emif_p0_acv_hard_io_pads.v(289): can't declare implicit net "dqs_busout" because the current value of 'default_...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Actually this is the error I get when I compile the C5G_LPDDR2_Nios_Test demonstration project:

Error: C5G_QSYS_mem_if_lpddr2_emif_p0_pin_map.tcl: Failed to find PLL reference clock

This is after converting to Quartus II 13.1 64 bit Windows 7.