compilation time

If compilation is stalling in Analysis & Synthesis (not 2% into the Fitter), you might have something like an inferred RAM that is hard for synthesis to deal with.

For inferred RAM in particular (your problem might be something else) more and more cases have been supported over the years, but there are probably still some cases that synthesis doesn't support like a certain combination of RAM control signals. I have had synthesis run a long time because the RTL implied a RAM, synthesis didn't support inference of that particular kind of RTL description for a RAM, and synthesis took a long time to implement it in regular registers.

If your code is in multiple source files and the problem is in synthesis, try synthesizing each file one at a time to see whether there is a problem that is isolated to a single file. The last synthesis message before the stall might give you a clue about the problem file, but the problem might be in the next file processed after the last one identified in the messages. If the problem is after the entire design has been elaborated, then the messages wouldn't be specific to a file anyway. To synthesize one portion of the design, set the top-level entity to the module or entity name for that portion in the "Top-level entity" field on the "General" page (top of the Category list) of the Settings dialog box. Synthesize the lowest-level blocks of hierarchy one at a time first, then those that instantiate lower-level blocks.