Honored Contributor
Honored ContributorThank you for the explanation.
According to your post, the correct way of instantiating this component should be: USE altera_mf_components.all; -- To avoid the local component declaration which is now removed from code. And following Port Map, for the ports to be connected to some signal (according to VHDL rules) PORT MAP ( wren_a => wren, clock0 => wrclock, clocken0 => wrclocken, clock1 => '0', clocken1 => '0', address_a => wraddress, address_b => rdaddress, rden_b => rden, data_a => wrdata, q_b => sub_wire0 ); We already have two if... generates: 1. IF CLOCK_MODE_ID = LEGACY_CLK_ID or CLOCK_MODE_ID = DUAL_CLK_ID GENERATE where generics are configured for dual clock and clock1 and clocken1 are connected to real signals. This is not causing problems. 2. IF CLOCK_MODE_ID = SINGLE_CLK_ID GENERATE where generics are configured for single clock and clock1 and clocken1 are causing this problem. Now connected to '0' to be strict to VHDL rules. In this configuration, Quartus reports this error: Error (272006): Connected clock1 port of the ALTSYNCRAM megafunction is unused with the current set of parameters Error (287078): Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled Warning (287013): Variable or input pin "wren_a" is defined but never used. Warning (287013): Variable or input pin "rden_b" is defined but never used. Warning (287013): Variable or input pin "data_a" is defined but never used. Warning (287013): Variable or input pin "address_a" is defined but never used. Warning (287013): Variable or input pin "address_b" is defined but never used. Warning (287013): Variable or input pin "clock0" is defined but never used. Warning (287013): Variable or input pin "clock1" is defined but never used. Warning (287013): Variable or input pin "clocken0" is defined but never used. Warning (287013): Variable or input pin "clocken1" is defined but never used. Some other hints?
