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Ah, now I understand. So, a "char" in your case is supposed to be a std_logic_vector with 8 bits, right?
But then, "commands" should be an
array of array of std_logic_vector(7 downto 0). You're missing one level of arrays. You try to initialize a std_logic_vector(7 downto 0) with "x"73746F700000", where "73746F700000" is 48 bits. I wonder why the compiler doesn't complain, but you have to fix that first.
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Yes. You are right. I need array of array - each member of array is array of chars - a command in the list. But how I should initialize it?
type commands is array(0 to 6) of std_logic_vector(7 downto 0);
signal commands_list : commands(0 to 2) :=
(
x"73746F700000", --stop
x"667764000000", --fwd
x"726576000000" --rev
);
if array(0 to 6) then x"73746F700000" is 7 elements 73 74 6F 70 00 00 00.
I was trying this way
signal commands_list : commands_l(2 downto 0) := (
0 => (0 => x"00", 1 => x"01", 2 => x"10", 3 => x"11", 4 => x"20", 5 => x"21"), --stop
1 => (0 => x"00", 1 => x"01", 2 => x"10", 3 => x"11", 4 => x"20", 5 => x"21"), --fwd
2 => (0 => x"00", 1 => x"01", 2 => x"10", 3 => x"11", 4 => x"20", 5 => x"21") --rev
);
But I get an error
Error (10515): VHDL type mismatch error at parser.vhd(71): std_ulogic type does not match string literal
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