Occasional ContributorCombinatorial node unexpectedly converted to register node.
Hi,
I have incorrect Fitter behavior using lpm_divide function.
I will upload full project design if needed, because this problem did not appear when I take the problematic part out from full project.
I will explain the problem step by step with screen shots:
181112g.png
I have placed lpm_divide with lpm_pipeline=0 that direct the fully combinatorial logic division.
Source registers that drive lpm_divide are InUseMul and Denom.
The lpm_divide does division with fully combinatorial.
The division result is captured by destination register named Rate.
181112h.png
Source and destination registers are both enabled every 8 clocks.
Because of this, lpm_divide need combinatorial delay less than 8 clock time.
181112i.png
To express these timing requirements, I have set set_muticycle_path assignment on these paths.
181112a.png
After I compile this project, I got timing error as this screen shot.
181112b.png
Find this setup violation on TimeQuest report.
From node is as depicted, and To node is Rate (Not depicted).
181112c.png
I investigated inside of lpm_divide, selnode node is combinatorial node as I set
lpm_pipeline=0 on lpm_divide. It is OK.
181112d.png
This is post mapping netlist view, selnose node is combinatorial here.
I see no register node inside lpm_divide. It is OK too.
181112e.png
This is post fitting netlist view, selnose node is converted to register node. I think it is illegal behavior of Fit.
The timing violation is reported from this node to Rate node.
Further experiment:
I tried many logic assignment on lpm_divide instances to block this conversion as below:
Netlist Optimizations=Never Allow
Automatic Asynchronous Signal Pipelining=Off
Optimization Technique=Area
Perform Physical Synthesis for Combinational Logic for Performance=Off
Perform WYSIWYG Primitive Resynthesis=Off
Restructure Multiplexers=Off
Timing-Driven Synthesis=Off
The result is only [Netlist Optimizations=Never Allow] does it work.
181112f.png
If I set [Netlist Optimizations=Never Allow] enabled, You can see no errors after fit.
I think some kind of automatic pipelining optimization improperly happens on my problem.
Quartus Prime 18.1.0 Build 625 Standard
regards,
