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Dear all
I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or Write) and one for switching (like a crossbar switch). To build up the network I need to connect these modules together via their inout data ports. I want to be able to transfer data bidirectionally. I have included my code at the end. This code just has two modules connected to each other.
- After synthesis in Quartus, ISE, or Synopsys Design Compiler or Synplify Pro, I get warnings which says there are a lot of nodes with combinational loop. But Why? Have I done anything wrong?
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Your entire design is asynchronous because there is no clock.
You use tristates in internal logic (not connected to I/O pins), and the fabric does not have internal tristates, so the synthesis tool attempts to implement your logic using multiplexers.
When it does that, because your design is asynchronous, combinatorial loops are created. If you look at the netlist output from the synthesis tool, you might see that.
The solution is to code this properly: don't use internal tristates, use proper muxes, and make sure you don't have logic loops.
Honored Contributor
