Combinational Loop In VHDL synthesis

The combinational loops are pretty clear. In your first assignment, PortL0 drives PortR0 and then in your third PortR0 drives PortL0. You of course intend the when clauses to make them mutually exclusive, but I doubt if the tools are that smart. You should use the proper VHDL constructs for mutually exclusive cases:

if(SW='0' and RW='0') then
  PortR0 <= ...
  PortR1 <= ...
  PortL0 <= ...
  PortL1 <= ...
elsif(SW='0' and RW='1') then
  ...
elsif(SW='1' and RW='0') then
 ...
else
 ...
end if;

	
	test_proc : process(RW, SW, PortR0, PortL0)
		variable sel : std_logic_vector(1 downto 0);
	begin
	
		sel := SW & RW;
	
		case sel is
		when "00" =>
			PortR0 <= PortL0;
			PortL0 <= 'Z';
		when "01" =>
			PortL0 <= PortR0;
			PortR0 <= 'Z';
		when others =>
			PortR0 <= 'Z';
			PortL0 <= 'Z';
		end case;
	
	end process;