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Altera_Forum
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8 years ago

Combinational Loop In VHDL synthesis

Dear all I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Ok - if it was fully synchronous then there should be no possibility of combinatorial loops - clearly something got missed. I can only reply to what is presented, and the code presented doesnt really seem to do much.

I suggested remapping the design with separate ins and outs, and only leaving the inouts at the top level where bi-directional pins exist.

is this interconnect internal or external to the FPGA?