Combinational Loop In VHDL synthesis

First thanks for your time and replies. Second please be patient. I'm here like anyone else to ask and learn. So, please, if this question is so shallow for you to answer, just ignore it.

It seems you don't get this is just a sample of a big design. As I said there is an interconnection network in my design. The purpose of this interconnection network is to connect some processors to some independent memories. This part of the design is just a combinational block which is placed between some registers.

Believe me, I know what synthesize-able VHDL code is. And yes, I've done everything on the paper first and then moved to coding. But as my background is in software coding, sometimes I get confused and think things are the same.

To be able to understand what the problem is, I just clipped a part of my code and presented it here.

I also know that I can have functional or behavioral simulation of my design. I've done it and it's fine. the vho netlist file is meant for post synthesis simulation.

And finally, the whole design is a synchronous clocked design.