Altera_Forum
Honored Contributor
18 years agoCoding Guidelines for VHDL and Verilog HDL
Many threads on the Altera Forum are about basic issues with synthesis like warnings, errors, and writing the HDL properly to synthesize the intended logic. If you need to know how to fix your HDL, start by checking whether it follows a recommended coding style for synthesis.
The purpose of this thread is for people to post HDL coding guideline references that they recommend and to comment on others' recommendations. The references can be books, links to information available on the Internet, code examples posted directly here, etc.