Code seems fine, can't find out where these errors are at. :(

Hi, I'm trying to make a vending machine project in VHDL for a class, and I keep getting errors that I can't resolve. I would really appreciate some advice!:

Error (10500): VHDL syntax error at vending_machine.vhd(21) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(36) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(38) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(51) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(53) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(66) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(68) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(81) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(83) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(96) near text "THEN"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at vending_machine.vhd(98) near text "THEN"; expecting "(", or "'", or "."

Here is my code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY vending_machine IS

PORT (clk, rst: IN STD_LOGIC;

nickel_in, dime_in, quarter_in: IN BOOLEAN;

candy_out, nickel_out, dime_out: OUT STD_LOGIC);

END vending_machine;

ARCHITECTURE fsm OF vending_machine IS

TYPE state IS (st0, st5, st10, st15, st20, st25, st30, st35, st40, st45);

SIGNAL pr_state, nx_state: state;

ATTRIBUTE enum_encoding: STRING;

ATTRIBUTE enum_encoding OF state: TYPE IS "sequential";

BEGIN

PROCESS (rst, clk)

BEGIN

IF (rst='1') THEN

pr_state <= st0;

ELSEIF (positive_edge(clk)) THEN

pr_state <= nx_state;

END if;

END PROCESS;

PROCESS (pr_state, nickel_in, dime_in, quarter_in)

BEGIN

CASE pr_state IS

WHEN st0 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in) THEN

nx_state <= st5;

ELSEIF (dime_in) THEN

nx_state <= st10;

ELSEIF (quarter_in) THEN

nx_state <= st25;

ELSE

nx_state <= st0;

END if;

WHEN st5 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in) THEN

nx_state <= st10;

ELSEIF (dime_in) THEN

nx_state <= st15;

ELSEIF (quarter_in) THEN

nx_state <= st30;

ELSE

nx_state <= st10;

END if;

WHEN st10 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in) THEN

nx_state <= st15;

ELSEIF (dime_in) THEN

nx_state <= st20;

ELSEIF (quarter_in) THEN

nx_state <= st35;

ELSE

nx_state <= st10;

END if;

WHEN st15 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in) THEN

nx_state <= st20;

ELSEIF (dime_in) THEN

nx_state <= st25;

ELSEIF (quarter_in) THEN

nx_state <= st40;

ELSE

nx_state <= st15;

END if;

WHEN st20 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '0';

IF (nickel_in) THEN

nx_state <= st25;

ELSEIF (dime_in) THEN

nx_state <= st30;

ELSEIF (quarter_in) THEN

nx_state <= st45;

ELSE

nx_state <= st20;

END if;

WHEN st25 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '0';

nx_state <= st0;

WHEN st30 =>

candy_out <= '1';

nickel_out <= '1';

dime_out <= '0';

nx_state <= st0;

WHEN st35 =>

candy_out <= '1';

nickel_out <= '0';

dime_out <= '1';

nx_state <= st0;

WHEN st40 =>

candy_out <= '0';

nickel_out <= '1';

dime_out <= '0';

nx_state <= st35;

WHEN st45 =>

candy_out <= '0';

nickel_out <= '0';

dime_out <= '1';

nx_state <= st35;

END CASE;

END PROCESS;

END fsm;