Code for 24 mhz to 434Khz..

Question

Hi ..

I have made one code for 24 mhz to 434Khz (Frequency divider)..

Actually in my project, i have 24 Mhz clock freqency and i want to convert it into 434 Khz...

My code is..

Library IEEE;

Use IEEE.std_logic_1164.all;

Entity FA is

port(clk :in bit;

clkout : out bit);

End Entity FA;

Architecture FA_calc of FA is

begin

process(clk)

variable cnt : integer range 0 to 28;

begin

if(clk'event and clk='1') then

if(cnt = 28 ) then

clkout<='1';

else

cnt := cnt+1;

clkout<='0';

end if;

end process;

End Architecture FA_calc;

Is it correct or not ??

ie cnt should be 28 or 56 ??

Thanks a lot..

altera_forum · Answer

Hi Satish,

You can create a simple testbench and run modelsim simulation for your code to see if it works as is expected. Or alternatively, you could create a test vector in Quartus II and do simulation in Quartus II as well.

altera_forum · Answer

It would be better to use a clock enable instead of a divided clock.  If you are going to use the divided clock, it is best for that clock to be global with no synchronous paths going to or from that clock domain.  Search this forum for "clock enable" to find my posts with comments on this.  http://www.alteraforum.com/forum/showthread.php?t=680 in particular has someone else's code example and my comments on changing it from a divided clock to a clock enable solution.

altera_forum · Answer

I saw your related post at http://www.alteraforum.com/forum/showthread.php?p=2411.  If you need a true 434 kHz clock waveform going to an output device pin and also need internal logic running at 434 kHz, you can still use a clock enable for the internal logic.  If that internal logic has to be synchronous to whatever is outside the FPGA using the 434 kHz clock driven out by the FPGA, then it might be better to use the true 434 kHz clock waveform internally.  However you do this, be careful with any paths crossing synchronously between clock domains.

altera_forum · Answer

Why do you not use a PLL and generate the internal and external freq.s in thge PLL device?

altera_forum · Answer

PLLs can generate 10 or 15 MHz minimum (for cyclone devices). The minimum output frequency of PLL varies with the targeted device. I think it would not be possible to get below 1 MHz using Altera device PLL. Hence, divide counter should serve the purpose in this case (for 434 KHz).

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Code for 24 mhz to 434Khz..

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