Clock uncertainty warnings under 10.0

Don't know the exact issue, but I strongly am against having Timequest write out your .sdc and using that. The .sdc should be like a source HDL file, i.e. something you edit and maintain and don't want a machine overwriting. If you want to use write sdc to get the syntax of something, I would write it to a dummy file and then cut and paste into yours. At the bare minimum, the .sdc file should have lots of comments to describe what the constraints are doing and how they were calculated.

All the time I see people get timing constraints(specifically from the Classic TAN) that have no supporting documentation. It will just be a Tsu constraint of 3ns. They have no idea how that was calculated, and if they're changing the FPGA, the upstream device or just doing a board re-spin, they either try to meet that old requirement but not knowing why, or have to re-do everything from scratch.

Sorry if that doesn't help your specific problem, but I think if you just kept derive_clock_uncertainty in your .sdc and nothing else, it should work.