Clock recovery violated: what to do?

Hi Rysc,

thank you so much for your fast reply!

I just downloaded your document about recovery and removal analysis, and I found it very useful indeed!

I'll read it more accurately in the next few days.

Regarding my design, it's a SOPC Builder design, so unfortunately I haven't full control on it. This is one of the reasons for which I don't like SOPC builder very much when something goes wrong.

The clock domain crossing is from the clock of the NIOS II (100 MHz), to the clock of a MCV filter (175 MHz). I sincerely don't know what is the function of the signal "testbed_EC102:my_system|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_oci_debug:the_cpu_nios2_oci_debug|resetrequest"

but by the name I think is something reset-related. Actually I don't think that my NIOS ever goes to request a reset to the hardware, but I'd like to get rid of this timing errors.

But, my question is, how can I do that if that's not my code, but Altera's one? The synchronizer is put there by SOPC builder, and I'm not very comfortable with the SOPC Builder-generated code, and I would not like to break things now (the design seems to work well).

Is declaring global/not global the signal coming to the affected synchronizer a viable option?

Thanks so much,

mantoz