Clock propagation delay between arrival and required path

Common Clock Path Pessimism Removal (CCPPR) is not difficult to understand but it has intrigued me why it is there in the first place. Shouldn't the tool take care of it rather than pass it as an option to enable or not. It sounds like the tool is saying "CCPPR should be removed but I leave it to you).

My guess is that it slows down the tool and so it could be just a commercial ploy as many designs will have enough margin anyway. If timing fails then enable it and wait longer.

In ASICs there is yet another pessimism; common clock convergence (CCP I think), keep making life difficult !