Clock, PLL, driver placement

As I said, I'm using Quartus Pro 18.0.1 and Quartus Pro 18.1. The error message is that the planner fails to place all clock buffers. In this design I have 6 10GE interfaces (Altera IP), two 40GE interfaces (altera again) a PCIe interface, and two custom Infiniband interfaces. One the same side there is a Uniphy QDRII memory interface. The other side of the device is used by two 12-channel Interlaken interfaces. Yes, the design is pretty dense. Now, I would expect if clock density were an issue it would have shown up in Quartus 18.0.1 Pro first. Since a clocking solution was resolved we thought everything was OK. But quartus 18.1 is complaining that it's having issues with SCLK Splines, placing a clock buffer on a regional clock net then trying to place another transmit clock in the same buffer as if it failed to consider both buffers at the same time or forgot about the first one it placed.

The next time I run it in 18.1.1 I'll grab the report file. Since this design contains custom IP I'll need to see if I can send it to you. Note that if I start stripping out interfaces things are fine so it's the entire design or nothing to get the issue to occur.

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