Clock network delay + internal cell delay > Minimum timing requirement

Hi Brad,

Yes your right, it did in fact route the signal non-globally to the 32 output registers. However the delay incurred was still considerably worse than for the global clock network.

I think we've pretty much reached the end of line, would you agree? Though i didn't fix my problem I've learnt a lot about the internal routing and clocking schemes. Thanks for the all the feedback!