Honored Contributor
Honored ContributorIn relation to Brads suggestion:
Info: Promoted node sclk_p (placed in PIN H2 (CLK0, LVDSCLK0p, Input)) Info: Promoted destinations to use location or clock signal Global Clock CLKCTRL_G0 Info: Following destination nodes may be non-global or may not use global or regional clocks Info: Destination node md_s[0] Info: Destination node md_s[1] Info: Destination node md_s[2] Info: Destination node md_s[3] Info: Destination node md_s[4] Info: Destination node md_s[5] Info: Destination node md_s[6] Info: Destination node md_s[7] Info: Destination node md_s[8] Info: Destination node md_s[9] Info: Non-global destination nodes limited to 10 nodes Seems as though this approach may not work as its limited to the number of nodes. I connected the clock (by wire) to another clock input pin (sclk_p2) and used it to clock the output I/O registers. I tried setting it to non-global signal, but the delay incurred was worse than for the global clock. So not sure if this approach will ever result in a saving simply because the address bus is quiet wide (32) and is spread out over the chip pins. In relation to Rysc's comment, timequest reports the setup time is breached for md_s -> md_p and oe_s -> md_p. So although i haven't explicitly given two tco requirements, timequest has split the tri-state output into the separate paths. So I guess i can ignore the oe_s > md_p violations since as you pointed out the bus is not required to turn around in one cycle. P.s. Sorry i wasn't sure what sort of information you were after, so it was basically just the top level of my project where the registered data bus I/O was.