--- Quote Start ---
The only thing i could think would be good if I could use a localized clock for my output registers and the global clock for all other logic.
--- Quote End ---
I don't ever use this capability, but the "Global Signal" assignment in the Assignment Editor supports point-to-point settings (both -from and -to fields used) so that you can control global usage for individual destinations. It worked for my QII 7.2 test case in point_to_point_global.zip.
In the test case, clk_in goes to 6 registers including 2 output registers in the I/O cell. With my "Global Signal" assignments, the clock had 4 global destinations for the internal registers and 3 nonglobal destinations for the 2 I/O cell registers plus the input to the global buffer.
generic_test_case.qsf has this:
--- Quote Start ---
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_in
set_instance_assignment -name GLOBAL_SIGNAL OFF -from clk_in -to dff_out*
--- Quote End ---
generic_test_case.fit.rpt has this:
--- Quote Start ---
+-----------------------------------------------------------------------------------------...+
; Control Signals ...;
+--------+----------+---------+-------+--------+----------------------+------------------+...+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;...;
+--------+----------+---------+-------+--------+----------------------+------------------+...+
; clk_in ; PIN_H2 ; 3 ; Clock ; no ; -- ; -- ;...;
; clk_in ; PIN_H2 ; 4 ; Clock ; yes ; Global Clock ; GCLK2 ;...;
+--------+----------+---------+-------+--------+----------------------+------------------+...+
+------------------------------------------------------------------------...+
; Global & Other Fast Signals ...;
+--------+----------+---------+----------------------+------------------+...+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;...;
+--------+----------+---------+----------------------+------------------+...+
; clk_in ; PIN_H2 ; 4 ; Global Clock ; GCLK2 ;...;
+--------+----------+---------+----------------------+------------------+...+
+--------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+----------------------------------------------+---------+
; Name ; Fan-Out ;
+----------------------------------------------+---------+
; clk_in ; 2 ;
. . .
+----------------------------------------------+---------+
. . .
+-----------------+
; Fitter Messages ;
+-----------------+
. . .
Info: Promoted node clk_in (placed in PIN H2 (CLK0, LVDSCLK0p, Input))
Info: Promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Following destination nodes may be non-global or may not use global or regional clocks
Info: Destination node dff_out1
Info: Destination node dff_out0
--- Quote End ---
The on-line help documenting this use of the "Global Signal" assignment:
--- Quote Start ---
Global Signal logic option
--------------------------------------------------------------------------------
This option can be set in the Assignment Editor.
A logic option that specifies whether the signal should be available throughout the device on the global routing paths. Global signals can be both pin- and logic-driven. Clock, output enable, register control, and memory control signals can be global signals. Turning on this option for a pin or a single-output logic function signal is equivalent to feeding the signal through a GLOBAL buffer. Turning off this option for a particular signal prevents any of the Auto Global options from using the signal as an automatic global signal.
This option can be set in the Assignment Editor. This option is available for all Altera devices supported by the Quartus II software.
You can select one of the following settings for these supported device (Arria GX, Cyclone, Cyclone II, Cyclone III, HardCopy II, MAX II, Stratix, Stratix II, Stratix II GX, Stratix III, and Stratix GX) families.
Priority Level: 1
Assignment Type/Location: Point-to-point assignment from source to destination (register or memory that is the intended global path).
Affected Path(s): Includes the path defined by source and destination.
Priority Level: 2
Assignment Type/Location: Single point assignment to any node.
Affected Path(s): Includes all fan-outs of the specified node.
For these supported device (Arria GX, HardCopy II, Stratix, Stratix II, Stratix II GX, Stratix III, and Stratix GX) families, a setting of on is equivalent to "global clock". Any "fast regional clock" and "dual-fast regional clock" clock assignments assigned to HardCopy II or Stratix II devices are converted to "regional clock" and "dual-regional clock", respectively.
--- Quote End ---
Honored Contributor
