Clock network delay + internal cell delay > Minimum timing requirement

Hi Rysc,

Thanks for the advice, I'll run the fast model analysis as well.

I don't think i can take it off global as it fans out to over 500 locations. The only thing i could think would be good if I could use a localized clock for my output registers and the global clock for all other logic. I don't know if this is possible though without the synthesizer removing it. I do happen to have another clock input free, i wonder if it would make any sense to input the system clock twice, once for logic and another for registering the outputs. I could then specify this second clock input as local, which may reduce the clock network delay. I'll give it a go. Thanks!