Clock network delay + internal cell delay > Minimum timing requirement

Sorry Rysc, i didn't see your reply. He's a simple drawing of my bus:

http://img120.imagevenue.com/img.php?image=01654_system_122_927lo.jpg

The delay between the CPU and FPGA is around 200ps.

The delay between the FPGA and RAM is also around 200ps.

The FPGA i'm using is the EP2C5F256C8.

There is no PLL (already both being used to generate audio clocks.)

I've uploaded an empty sample project, basically with the *.qsf assignments and the top level of vhdl (just a wrapper where i register the data outputs).

My timing problem occurs on the output of registered data on the I/O pins md_p[0 .. 31].

Basically all the delay is within the fast output register at the pin, and so theres simply nothing i can do to reduce that delay except make sure the clock gets there sooner (or equivalently to the ram later.)

Thanks for helping anyway, I think i'll be pushing for a faster speed grade.