Clock network delay + internal cell delay > Minimum timing requirement

Agreed. Going above 100MHz without a PLL is pretty fast. Another problem of not having a PLL is your variance over slow/fast timing models. Static timing analysis does a default slow model timing analysis, but you'll also want to run a fast model analysis, and now that all your delays can vary over this range with Process/Voltage/Temperature. The PLL not only removes the global clock tree delay, it removes it in a PVT invariant way, so that your timing analysis volitility is reduced.

Note that reducing the fanout shouldn't make much of a difference. The global trees are pre-laid out and rebuffered throughout, so most of the loading will be on side branches that have minimal capacitive affect.

Did you try taking the clock off a global? (You may have responded to this, but the thread is getting long.)

Also, if you're failing by 200-300ps, I can say almost without a doubt that your interface should work on a nominal board(you're not at the worst case PVT corner, so all the delays will be faster than the slow model reports). If you're seeing failures, I think something else is going wrong.