Clock network delay + internal cell delay > Minimum timing requirement

Thanks for your suggestion Brad, but unfortunately the clock is generated by the CPU, which also requires access to memory.

I have come to my conclusion, and that is there are only two solutions to this problem:

- Increase the track length of the clock from the FPGA to the RAM (to delay the clock by the required 200-300 ps relative to the data)

- Move to the next speed grade (-7)

I talked to my altera representative and he basically confirmed these timing problems are inherent limits with my device. He also suggested i ensure the global system clock only feeds into clock inputs of LEs, as otherwise this can increase the clock network delay substantially. So having done everything possible I'll have to ask my superiors what action to take.

So my advice to anyone implementing a system synchronous data bus, make sure you have a pll free!

Thanks for your suggestions Brad and Rysc.