Clock network delay + internal cell delay > Minimum timing requirement

Can you attach a sample design and identify which pins the data is going out on? Please make it as similar as possible, i.e. the same device you're using, with clock and data pins assigned to the same pins, and the PLL configured the same way? Also, in a sentence or two, give a quick description of how the clock drives the FPGA, how it drives the upstream device, the upstream device's requirements, and the board delay from the FPGA to the upstream device? This shouldn't be too hard, but I think we're having difficulty trying to describe what's occuring with words rather than just doing an actual design. I'm out tomorrow, but will take a look at it the next day and get something back to you. This way we have something we can all work from. Thanks.