Clock network delay + internal cell delay > Minimum timing requirement

I didn't think through your previous post well enough and got the wrong idea. I was thinking you meant that you rerouted the clock to a different pin to drive it out to the SDRAM.

Since you've already been willing to modify the board, maybe you should go ahead and change the clock to a source-synchronous output (what I wrongly thought you did). If the only thing connected to the SDRAM is the FPGA (SDRAM buses not also accessed by something else), if the board connections allow this kind of change, and if the timing analysis says that's better, it might be worth the trouble.