Clock network delay + internal cell delay > Minimum timing requirement

But i'm still using an external clock input? The only difference is now i'm phase shifting that input clock to counter the global clock network delay. Its still driving all the internal logic and launching the data.

While in principal this idea should have worked, i found through experimentation the delays given by time quest did not represent measured delays at the output. This meant the amount by which i was phase shifting the clock was unknown and was unreliable (data corruption resulted). So i've scrapped the whole idea and i'm back to square one.