Clock network delay + internal cell delay > Minimum timing requirement

Well I believe I've found a solution, though I had to mod the board. I've re-routed (externally) the system synchronous clock to a Dual-Purpose DPCLK/DQS pin (previously using a LVDSCLK input). These pins have "dedicated DQS phase shift circuitry" that can be used to delay the clock. I've played around with the delay parameter and can achieve a global clock network delay anywhere from 2.7ns to 6.5ns. Since the period of my clock is 7.5ns, neither of these delays is great enough to solve my problem, and so i've used a delay value of ~4ns and inverted the clock, to achieve an effective phase shift that should negate the global clock network delay.

My only problem now is how to configure time quest to report based on the new delayed + inverted clock. Time quest has obviously detected i'm using an inverted clock and is now reporting everything based on the falling edge of the original clock. Does anyone know how i can avoid this? I'd like it to treat the new clock as if it was an external input, and not derived from the original clock input.

Thanks for your time, esp Brad and Rysc.