Clock network delay + internal cell delay > Minimum timing requirement

Apologies for the confusion, I obviously didn't understand the use of the reference pin command. I'm using a system-synchronous clock setup:

http://img104.imagevenue.com/img.php?image=60343_timing_problems_122_1170lo.jpg

From what i can see, i should still be able to use the inverted clock to launch the data, as long as i can ensure enough delay for Tco min:

http://img185.imagevenue.com/img.php?image=61160_phase_delay_122_139lo.jpg

Looking at the first picture i posted:

http://img120.imagevenue.com/img.php..._122_747lo.jpg

The clock network delay + data delay values should ensure that the hold and setup times are met.

Would this seem correct? There's two issues i can see with implementing this, the first being ensuring i can register the data within half a clock cycle on the inverted clock and the other being how to configure the SDC constraints to recognize what i'm doing.

Thanks for you feedback.