Clock network delay + internal cell delay > Minimum timing requirement

I was basing my statement solely off the fact that you were using the -reference_pin option. This generally means you're sending a clock off chip alongside the data(the clock is sclk_p and the data is md_p*). In this scenario, much of the clock delay inside the FPGA cancels itself out. For example, if the clock tree is 2.7ns, it takes ~2.7ns to get to the data output register and ~2.7ns to get the clock to the port where it leaves the chip. These cancel each other out in the timing analysis(so if they were 100ns delays, you could still meet timing). Source synchronous often allows higher-speeds to be achieved because a lot of the variation tends to cancel out. Is a source synchronous interface what you're doing, or do you have a board oscillator that feeds the FPGA and the SDRAM?

One thing I don't see, and it might be there but I just can't tell in the waveform, is if the delay to sclk_p in the data required time being removed. I'm not sure exactly how it's shown there, but it looks like your latch edge is at 7.5ns and doesn't move from there.