Clock network delay + internal cell delay > Minimum timing requirement

I had to install 7.2 to get the wave viewer, but its very useful. I can see that my original values were correct, and the max output delay should be set 1.5ns, as you can see from this screenshot:

http://img120.imagevenue.com/img.php?image=89373_timing_diagram_122_747lo.jpg

Why does the clock delay not play a part, seeing as the clock is external to both the FPGA and the RAM?

Is it common practice to invert the launch clock (and delay it) to achieve setup times? I can see this getting messy.