Clock network delay + internal cell delay > Minimum timing requirement

On first glance, looks correct to me, but hard to say without knowing all the details of the the design, layout, clocking scheme, etc.. I didn't realize that you were doing a source synchronous interface. If that's the case, then clock delay generally doesn't play a part, you just want to make sure your clock and data come out with the proper relationship. This makes the write side pretty easy to meet(often you have to do a phase shift on the clock if, for example, it needs to be 90 degrees or something from the data). Usually the read side is the more difficult interface, but it looks like you're on the right track.

Look at the waveform shown in TimeQuest on a single data output(both the setup and hold waveform on that output). See if what its showing you correlates to what you expect to happen(and the slack basically says, my delay could vary by this much and I would still have a successful transfer). Source synch interfaces are one thing that, for the life of me, I can't just look at someone's constraints and understand. I still have to draw it out every time and say, does that look right?