Clock network delay + internal cell delay > Minimum timing requirement

Thanks for the advice Brad and Rysc, I've gone back and reviewed my timing constraints in my SDC file. I think i've incorrectly put the setup time where the max tco should be.

Here's what i've got now:

set_output_delay -add_delay -clock [get_clocks {clk_133}] -reference_pin sclk_p -min -0.800 [get_ports md_p*]

set_output_delay -add_delay -clock [get_clocks {clk_133}] -reference_pin sclk_p -max 6.000 [get_ports md_p*]

With a system clock of 133MHz (7.5ns period), would these would correspond to the RAM requirements of a hold time of 0.8ns and a setup time of 1.5ns? If so then i don't have any timing problems and I'd be very happy!