Clock network delay + internal cell delay > Minimum timing requirement

If anything, the limitation is on the number of PLLs. All devices have long clock tree delays, and they actually get longer in the higher-end parts, but the PLLs are designed to counteract this.

At those speeds, you may want to take the clock off a global, especially if the source is anywhere near the SDRAM interface. Local routing can actually be faster, getting you a faster output, but you will get more skew across the bus since local routing is not de-skewed like a global tree. This output skew may be perfectly acceptable though.