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Altera_Forum's avatar
Altera_Forum
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18 years ago

Clock network delay + internal cell delay > Minimum timing requirement

Hi, I have a SDRAM controller running at 133MHZ which is currently violating the setup requirements of the RAM. I have a register connected to an I/O pin which tri-states the data bus when the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The output delay chain is probably already at its fastest setting, but that's something to check.

Consider using a PLL to shift the clock of the output registers to reduce the FPGA tco.