Occasional Contributor
Super ContributorHi,
HDMI_TX_CLK is an output clock. The timing analyzer does not automatically include them in the internal setup timing analysis unless there is a specific output delay constraint.
Without an explicit constraint, the tool may not consider the output clock when analyzing internal data paths since it assumes the clock is external and isn't used for internal synchronization.
By applying source synchronous output constraint (ie. set_output_delay), you effectively guide the timing analyzer to check that the data arrives at the output in sync with HDMI_TX_CLK, and the required setup and hold times are met. As a result, HDMI_TX_CLK will appear in the setup report since it now plays a crucial role in determining whether the output timing meets your design's requirements.
You may check this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-tq-ea-ss-out.html for an example of source synchronous output constraint. There're more details in document AN433.
Thanks,
Regards,
Sheng
Occasional ContributorAs explained I had changed the design in the design file I gave you such there was an internal clock signal TX_PCLK that went through an IO buffer in an attempt to separate the pin signal HDMI_TX_CLK and the internal clock.
TX_PCLK is what was the old HDMI_TX_CLK. Sorry for any confusion.
