Honored Contributorhey all.
i am using the 1-port single clock ram present in LPM megafunctions . simulating the function shows that the clock is positive-edge triggered. i wish to use a negative edge-triggered clock for it. is there a way to set the clock this way? thanks!
Honored ContributorIf using Quartus integrated synthesis, simply invert the clock in the RTL or schematic before the connection to the megafunction port. Quartus will move the inverter into the RAM block during compilation.
If you use incremental compilation, the inverter in the source code needs to be in the same design partition with the RAM megafunction to avoid having the inversion done in an LE LUT.Honored Contributorthanks Brad!
