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TimeQuest Timing Analyser
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# The following multicycle applies to all paths ending at registers clocked by clk
set_multicycle_path -to [get_clocks clk] 2
I found this in the QuartusII Handbook (Chapter TimeQuest Timing Analyzer). There a
lot more API's. :)
For Gated clocks you can specify generated_clocks based on the edges of the masterclock.
1 is first rising edge
2 is first falling edge
3 is second rising edge
4 is second falling edge
5 is third rising edge
......
1 3 5 defines a clock with half of period of the master clock.
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