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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clock gating with enable or not

Here is a n00b question from one which is rusty in VHDL: The statement is not to gate the clock, but is the following considered clock gating? ena is a synchronous enable signal. proces...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

finally, i found who is responible for such situation. Among 80 global assignments we have Auto Clock Enable Replacement which("witch") is on by default.

So default assignments is very smart , smarter than required.