Clock frequency vs. Latency issues for an IIR filter

Dear makon,

you're quite welcome.

A few final words of advice.

First, learning how to perform static timing analysis is quite important to know that your design can actually meet your requirements, ie, that it can

actually run at the frequency you require.

http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf

Second, you can also instance megafunctions from Verilog/VHDL code. You don't have to resort to BDF for that -- that's how people like me get by without BDF.

Finally, the synthesis tools can recognize many specific functions from Verilog/VHDL code and infer the usage of optimized functions.

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

That includes integer adders, multipliers -- including pipelining -- and a lot of other things.

Of course, there'll also be cases where that's not true and you need to instance specific megafunctions.