Honored Contributor
Honored ContributorThat's great ... thanks again rbugalho.
--- Quote Start --- if you register both the inputs and outputs, you have a 2 cycle latency. This will work for sure at 20MHz. --- Quote End --- Earlier I was pipelining each module to 1 clock-cycle latency, and was getting an overall input-to-output latency of about 8 clock-cycles. ( I have a few more things apart from that equation). So this new value of latency (2) is a significant achievement ! --- Quote Start --- Actually, I did a quick implementation of that equation on a Cyclone III, with all the factors being registers, and the fMax is 93MHz. --- Quote End --- I appreciate you taking that effort for me. And making me aware that even such an analysis can be done. Will surely learn it in the future. Right now I need to get working with my controller. --- Quote Start --- Quite honestly, I never use BDF, so I'm totally unfamiliar with it. But yes, it should be related to pipelining options or registered input/output options. --- Quote End --- The reason I was using a .BDF file, because I wanted to use Megafunctions instead of simple Verilog constructs. I hear that they are well optimized. ( ref: "using megafunction vs just verilog expression" http://www.alteraforum.com/forum/showthread.php?t=22128 (http://http://www.alteraforum.com/forum/showthread.php?t=22128) ) And yes, when I did remove the "pipelining" option from those Megafunctions - the clock input simply vanished. So I guess, this is what I require ! Moreover, since I do not require pipelining now, I can use simple constructs like A*B, and do away with the need for Megafunctions. Which translates to the ability to code everything in Verilog, and not use a BDF file. Wow ! You solved so many of my complications in so less time. Cheers :-)
